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1/19 january 2002 m27c160 16 mbit (2mb x 8 or 1mb x 16) uv eprom and otp eprom n 5v 10% supply voltage in read operation n access time: 50ns n byte-wide or word-wide configurable n 16 mbit mask rom replacement n low power consumption C active current 70ma at 8mhz C standby current 100a n programming voltage: 12.5v 0.25v n programming time: 50s/word n electronic signature C manufacturer code: 20h C device code: b1h description the m27c160 is a 16 mbit eprom offered in the two ranges uv (ultra violet erase) and otp (one time programmable). it is ideally suited for micro- processor systems requiring large data or program storage and is organised as either 2 mbit words of 8 bit or 1 mbit words of 16 bit. the pin-out is com- patible with a 16 mbit mask rom. the fdip42w (window ceramic frit-seal package) has a transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. a new pattern can then be written rapidly to the device by following the programming proce- dure. for applications where the content is programmed only one time and erasure is not required, the m27c160 is offered in pdip42, sdip42, plcc44 and so44 packages. 44 1 1 42 1 42 fdip42w (f) so44 (m) pdip42 (b) plcc44 (k) sdip42 (s) 1 42 figure 1. logic diagram ai00739b 20 a0-a19 bytev pp q0-q14 v cc m27c160 g e v ss 15 q15aC1
m27c160 2/19 figure 3. plcc connections ai03012 a11 a14 q7 q5 23 q0 q8 q1 q9 q2 nc q12 a4 a0 e v ss a3 a2 12 a10 a16 1 a7 bytev pp a13 a5 q6 44 v ss a9 m27c160 a6 a12 q13 v ss q14 34 q10 a1 a15 q15aC1 g q3 q11 v cc q4 a18 a17 a8 a19 figure 2. dip connections g q0 q8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 q7 a12 a16 bytev pp q15a-1 q5 q2 q3 v cc q11 q4 q14 a9 a8 a17 a4 a18 a19 a7 ai00740 m27c160 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 q1 q9 a6 a5 q6 q13 42 39 38 37 36 35 34 33 a11 a10 q10 21 q12 40 41 figure 4. so connections g q0 q8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 q7 a12 a16 bytev pp q15a-1 q5 q2 q3 v cc q11 q4 q14 a9 a19 a18 a4 nc nc a7 ai01264 m27c160 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 q1 q9 a6 a5 q6 q13 44 39 38 37 36 35 34 33 a11 a10 q10 21 q12 40 43 1 42 41 a17 a8 table 1. signal names a0-a19 address inputs q0-q7 data outputs q8-q14 data outputs q15aC1 data output / address input e chip enable g output enable byte v pp byte mode / program supply v cc supply voltage v ss ground nc not connected internally
3/19 m27c160 table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum dc voltage on input or output is C0.5v with possible undershoot to C2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5vwithpossibleovershoottov cc +2v for a period less than 20ns. 3. depends on range. table 3. operating modes note: x = v ih or v il ,v id = 12v 0.5v. table 4. electronic signature note: outputs q15-q8 are set to '0'. symbol parameter value unit t a ambient operating temperature (3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage (except a9) C2 to 7 v v cc supply voltage C2 to 7 v v a9 (2) a9 voltage C2 to 13.5 v v pp program supply voltage C2 to 14 v mode e g byte v pp a9 q15aC1 q8-q14 q7-q0 read word-wide v il v il v ih x data out data out data out read byte-wide upper v il v il v il x v ih hi-z data out read byte-wide lower v il v il v il x v il hi-z data out output disable v il v ih x x hi-z hi-z hi-z program v il pulse v ih v pp x data in data in data in verify v ih v il v pp x data out data out data out program inhibit v ih v ih v pp x hi-z hi-z hi-z standby v ih x x x hi-z hi-z hi-z electronic signature v il v il v ih v id code codes codes identifier a0 q7 q6 q5 q4 q3 q2 q1 q0 hex data manufacturers code v il 00100000 20h device code v ih 10110001 b1h
m27c160 4/19 device operation the operating modes of the m27c160 are listed in the operating modes table. a single power supply is required in the read mode. all inputs are ttl compatible except for v pp and 12v on a9 for the electronic signature. read mode the m27c160 has two organisations, word-wide and byte-wide. the organisation is selected by the signal level on the byte v pp pin. when byte v pp is at v ih the word-wide organisation is selected and the q15aC1 pin is used for q15 data output. when the byte v pp pin is at v il the byte-wide or- ganisation is selected and the q15aC1 pin is used for the address input aC1. when the memory is logically regarded as 16 bit wide, but read in the byte-wide organisation, then with aC1 at v il the lower 8 bits of the 16 bit data are selected and with aC1 at v ih the upper 8 bits of the 16 bit data are selected. the m27c160 has two control functions, both of which must be logically active in order to obtain data at the outputs. in addition the word-wide or byte- wide organisation must be selected. chip enable (e ) is the power control and should be used for device selection. output enable (g )isthe output control and should be used to gate data to the output pins independent of device selection. assuming that the addresses are stable, the ad- dress access time (t avqv ) is equal to the delay from e to output (t elqv ). data is available at the output after a delay of t glqv from the falling edge of g , assuming that e has been low and the ad- dresses have been stable for at least t avqv -t glqv . table 5. ac measurement conditions high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v figure 5. ac testing input output waveform ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 6. ac testing load circuit ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test table 6. capacitance (1) (t a =25c,f=1mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance (except byte v pp )v in =0v 10 pf input capacitance (byte v pp )v in =0v 120 pf c out output capacitance v out =0v 12 pf
5/19 m27c160 table 7. read mode dc characteristics (1) (t a =0to70corC40to85c;v cc = 5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 10 a i cc supply current e =v il ,g =v il , i out = 0ma, f = 8mhz 70 ma e =v il ,g =v il , i out = 0ma, f = 5mhz 50 ma i cc1 supply current (standby) ttl e =v ih 1ma i cc2 supply current (standby) cmos e >v cc C 0.2v 100 a i pp program current v pp =v cc 10 a v il input low voltage C0.3 0.8 v v ih (2) input high voltage 2 v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C400a 2.4 v standby mode the m27c160 has a standby mode which reduces the active current from 50ma to 100a. the m27c160 is placed in the standby mode by apply- ing a cmos high signal to the e input. when in the standby mode, the outputs are in a high imped- ance state, independent of the g input. two line output control because eproms are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. the two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficient use of these two control lines, e should be decoded and used as the prima- ry device selecting function, while g should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the supplies to the devices. the supply current i cc has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of e . the magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device outputs. the associated transient voltage peaks can be suppressed by complying with the two line output control and by properly se- lected decoupling capacitors. it is recommended that a 0.1f ceramic capacitor is used on every device between v cc and v ss . this should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. in addition, a 4.7f electrolytic capacitor should be used between v cc and v ss for every eight devices. this capacitor should be mounted near the power supply connection point. the purpose of this ca- pacitor is to overcome the voltage drop caused by the inductive effects of pcb traces.
m27c160 6/19 table 8. read mode ac characteristics (1) (t a =0to70corC40to85c;v cc = 5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp. 2. sampled only, not 100% tested. 3. speed obtained with high speed ac measurement conditions. symbol alt parameter test condition m27c160 unit -50 (3) -70 (3) min max min max t avqv t acc address valid to output valid e =v il ,g =v il 50 70 ns t bhqv t st byte high to output valid e =v il ,g =v il 50 70 ns t elqv t ce chip enable low to output valid g =v il 50 70 ns t glqv t oe output enable low to output valid e =v il 30 35 ns t blqz (2) t std byte low to output hi-z e =v il ,g =v il 30 30 ns t ehqz (2) t df chip enable high to output hi-z g =v il 0 25 0 25 ns t ghqz (2) t df output enable high to outputhi-z e =v il 0 25 0 25 ns t axqx t oh address transition to output transition e =v il ,g =v il 55ns t blqx t oh byte low to output transition e =v il ,g =v il 55ns
7/19 m27c160 table 9. read mode ac characteristics (1) (t a =0to70corC40to85c;v cc = 5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp. 2. sampled only, not 100% tested. 3. speed obtained with high speed ac measurement conditions. symbol alt parameter test condition m27c160 unit -90 -100 -120/-150 min max min max min max t avqv t acc address valid to output valid e =v il ,g =v il 90 100 120 ns t bhqv t st byte high to output valid e =v il ,g =v il 90 100 120 ns t elqv t ce chip enable low to output valid g =v il 90 100 120 ns t glqv t oe output enable low to output valid e =v il 45 50 60 ns t blqz (2) t std byte low to output hi-z e =v il ,g =v il 30 40 50 ns t ehqz (2) t df chip enable high to output hi-z g =v il 030040050ns t ghqz (2) t df output enable high to outputhi-z e =v il 030040050ns t axqx t oh address transition to output transition e =v il ,g =v il 555ns t blqx t oh byte low to output transition e =v il ,g =v il 555ns figure 7. word-wide read mode ac waveforms note: byte v pp =v ih . ai00741b taxqx tehqz a0-a19 e g q0-q15 tavqv tghqz tglqv telqv valid hi-z valid
m27c160 8/19 figure 8. byte-wide read mode ac waveforms note: byte v pp =v il . figure 9. byte transition ac waveforms note: chip enable (e ) and output enable (g )=v il . ai00742b taxqx tehqz aC1,a0-a19 e g q0-q7 tavqv tghqz tglqv telqv valid hi-z valid ai00743c taxqx tbhqv a0-a19 bytev pp tavqv tblqx tblqz valid hi-z aC1 data out data out valid q0-q7 q8-q15
9/19 m27c160 table 10. programming mode dc characteristics (1) (t a =25c;v cc = 6.25v 0.25v; v pp = 12.5v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . table 11. programming mode ac characteristics (1) (t a =25c;v cc = 6.25v 0.25v; v pp = 12.5v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0 v in v cc 1 m a i cc supply current 50 ma i pp program current e =v il 50 ma v il input low voltage C0.3 0.8 v v ih input high voltage 2.4 v cc +0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C2.5ma 3.5 v v id a9 voltage 11.5 12.5 v symbol alt parameter test condition min max unit t avel t as address valid to chip enable low 2 s t qvel t ds input valid to chip enable low 2 s t vphav t vps v pp high to address valid 2s t vchav t vcs v cc high to address valid 2s t eleh t pw chip enable program pulse width 45 55 s t ehqx t dh chip enable high to input transition 2 s t qxgl t oes input transition to output enable low 2 s t glqv t oe output enable low to output valid 120 ns t ghqz (2) t dfp output enable high to output hi-z 0 130 ns t ghax t ah output enable high to address transition 0ns programming when delivered (and after each erasure for uv eprom), all bits of the m27c160 are in the '1' state. data is introduced by selectively program- ming '0's into the desired bit locations. although only '0's will be programmed, both '1's and '0's can be present in the data word. the only way to change a '0' to a '1' is by die exposure to ultraviolet light (uv eprom). the m27c160 is in the pro- gramming mode when v pp input is at 12.5v, g is at v ih and e is pulsed to v il .thedatatobepro- grammed is applied to 16 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. v cc is specified to be 6.25v 0.25v.
m27c160 10/19 presto iii programming algorithm the presto iii programming algorithm allows the whole array to be programed with a guaran- teed margin in a typical time of 52.5 seconds. pro- gramming with presto iii consists of applying a sequence of 50s program pulses to each word until a correct verify occurs (see figure 11). during programing and verify operation a margin mode circuit is automatically activated to guaran- tee that each cell is programed with enough mar- gin. no overprogram pulse is applied since the verify in margin mode provides the necessary margin to each programmed cell. program inhibit programming of multiple m27c160s in parallel with different data is also easily accomplished. ex- cept for e , all like inputs including g of the parallel m27c160 may be common. a ttl low level pulse applied to a m27c160's e input and v pp at 12.5v, will program that m27c160. a high level e input in- hibits the other m27c160s from being pro- grammed. program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. the verify is accomplished with e at v ih and g at v il ,v pp at 12.5v and v cc at 6.25v. figure 10. programming and verify modes ac waveforms tavel valid ai00744 a0-a19 q0-q15 bytev pp v cc g data in data out e tqvel tvphav tvchav tehqx teleh tglqv tqxgl tghqz tghax program verify figure 11. programming flowchart ai01044b n = 0 last addr verify e = 50 m s pulse ++n = 25 ++ addr v cc = 6.25v, v pp = 12.5v fail check all words bytev pp =v ih 1st: v cc = 6v 2nd: v cc = 4.2v yes no yes no yes no
11/19 m27c160 electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the es mode is functional in the 25c 5c am- bient temperature range that is required when pro- gramming the m27c160. to activate the es mode, the programming equipment must force 11.5v to 12.5v on address line a9 of the m27c160, with v pp =v cc = 5v. two identifier bytes may then be sequenced from the device out- puts by toggling address line a0 from v il to v ih .all other address lines must be held at v il during electronic signature mode. byte 0 (a0 = v il ) rep- resents the manufacturer code and byte 1 (a0 = v ih ) the device identifier code. for the st- microelectronics m27c160, these two identifier bytes are given in table 4 and can be read-out on outputs q7 to q0. erasure operation (applies to uv eprom) the erasure characteristics of the m27c160 is such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 ?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 ? range. research shows that constant exposure to room level fluo- rescent lighting could erase a typical m27c160 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the m27c160 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the m27c160 window to prevent unintentional era- sure. the recommended erasure procedure for m27c160 is exposure to short wave ultraviolet light which has a wavelength of 2537 ?. the inte- grated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 30 w-sec/cm 2. the erasure time with this dosage is approximate- ly 30 to 40 minutes using an ultraviolet lamp with 12000 w/cm 2 power rating. the m27c160 should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be removed before erasure.
m27c160 12/19 table 12. ordering information scheme note: 1. high speed, see ac characteristics section for further information. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m27c160 -70 x m 1 tr device type m27 supply voltage c=5v device function 160 = 16 mbit (2mb x 8 or 1mb x 16) speed -50 (1) =50ns -70 (1) =70ns -90 = 90 ns -100 = 100 ns -120 = 120 ns -150 = 150 ns v cc tolerance blank = 10% x=5% package f = fdip42w b = pdip42 s = sdip42 k = plcc44 m = so44 temperature range 1 = 0 to 70 c 6 = C40 to 85 c options tr = tape & reel packing
13/19 m27c160 table 13. revision history date version revision details january 1999 -01 first issue 20-sep-00 -02 an620 reference removed 19-jul-01 -03 sdip42 package added 17-jan-02 -04 50ns speed class added, so44 package mechanical data and drawing clarified
m27c160 14/19 table 14. fdip42w - 42 pin ceramic frit-seal dip, with window, package mechanical data symbol mm inches typ min max typ min max a 5.72 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 0.177 b 0.41 0.56 0.016 0.022 b1 1.45 C C 0.057 C C c 0.23 0.30 0.009 0.012 d 54.41 54.86 2.142 2.160 d2 50.80 C C 2.000 C C e 15.24 C C 0.600 C C e1 14.50 14.90 0.571 0.587 e 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 16.18 18.03 0.637 0.710 l 3.18 0.125 s 1.52 2.49 0.060 0.098 k 9.40 C C 0.370 C C k1 11.43 C C 0.450 C C a 4 11 4 11 n42 42 figure 12. fdip42w - 42 pin ceramic frit-seal dip, with window, package outline drawing is not to scale. fdipw-b a3 a1 a l b1 b e1 d s e1 e n 1 c ea d2 k k1 a eb a2
15/19 m27c160 table 15. pdip42 - 42 pin plastic dual in line, 600 mils width, package mechanical data symbol mm inches typ min max typ min max a C 5.08 C 0.200 a1 0.25 C 0.010 C a2 3.56 4.06 0.140 0.160 b 0.38 0.53 0.015 0.021 b1 1.27 1.65 0.050 0.065 c 0.20 0.36 0.008 0.014 d 52.20 52.71 2.055 2.075 d2 50.80 C C 2.000 C C e 15.24 C C 0.600 C C e1 13.59 13.84 0.535 0.545 e1 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 0.86 1.37 0.034 0.054 a 0 10 0 10 n42 42 figure 13. pdip42 - 42 pin plastic dual in line, 600 mils width, package outline drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
m27c160 16/19 table 16. sdip42 - 42 pin shrink plastic dip, 600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a 5.08 0.200 a1 0.51 0.020 a2 3.81 3.05 4.57 0.150 0.120 0.180 b 0.46 0.38 0.56 0.018 0.015 0.022 b2 1.02 0.89 1.14 0.040 0.035 0.045 c 0.25 0.23 0.38 0.010 0.009 0.015 d 36.83 36.58 37.08 1.450 1.440 1.460 e 1.78 C C 0.070 C C e 15.24 16.00 0.600 0.630 e1 13.72 12.70 14.48 0.540 0.500 0.570 ea 15.24 C C 0.600 C C eb 18.54 0.730 l 3.30 2.54 3.56 0.130 0.100 0.140 s 0.64 0.025 n42 42 figure 14. sdip42 - 42 pin shrink plastic dip, 600 mils width, package outline drawing is not to scale. sdip a2 a1 a l b2 b e d s e1 e n 1 c ea eb d2
17/19 m27c160 table 17. plcc44 - 44 lead plastic leaded chip carrier, package mechanical data symbol mm inches typ min max typ min max a 4.20 4.70 0.165 0.185 a1 2.29 3.04 0.090 0.120 a2 C 0.51 C 0.020 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 17.40 17.65 0.685 0.695 d1 16.51 16.66 0.650 0.656 d2 14.99 16.00 0.590 0.630 e 17.40 17.65 0.685 0.695 e1 16.51 16.66 0.650 0.656 e2 14.99 16.00 0.590 0.630 e 1.27 C C 0.050 C C f 0.00 0.25 0.000 0.010 r 0.89 C C 0.035 C C n44 44 cp 0.10 0.004 figure 15. plcc44 - 44 lead plastic leaded chip carrier, package outline drawing is not to scale. plcc d ne e1 e 1 n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2
m27c160 18/19 table 18. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data millimeters inches symbol typ min max typ min max a 2.80 0.1102 a1 0.10 0.0039 a2 2.30 2.20 2.40 0.0906 0.0866 0.0945 b 0.40 0.35 0.50 0.0157 0.0138 0.0197 c 0.15 0.10 0.20 0.0059 0.0039 0.0079 cp 0.08 0.0030 d 28.20 28.00 28.40 1.1102 1.1024 1.1181 e 13.30 13.20 13.50 0.5236 0.5197 0.5315 e 1.27 C C 0.0500 C C he 16.00 15.75 16.25 0.6299 0.6201 0.6398 l 0.80 0.0315 n44 44 a 8 8 figure 16. so44 - 44 lead plastic small outline, 525 mils body width, package outline drawing is not to scale. so-d e n d c l a1 a eh a 1 e cp b a2
19/19 m27c160 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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